1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of designing the same. More particularly, the present invention relates to a design-for-testability technology based on scan design.
2. Description of the Related Art
Semiconductor integrated circuits are tested after the manufacture to detect malfunctions of the circuits, such as delay faults and stuck-at faults. One known integrated circuit design technique for improving testability is to incorporate test circuits into the circuits to be designed. Such design technique is often referred to as design for testability (DFT).
The scan design is one of the known design-for-testability techniques. In a semiconductor integrated circuit based on the scan design, all or some of the flip-flops within the circuit to be designed are replaced with scan flip-flops. In the test, the scan flip-flops are operated to form a scan chain (or a scan path) and the scan test is carried out by entering a test pattern and reading the states of the flip-flops through the scan path.
In the development of a semiconductor integrated circuit, the change of the function of the circuit may be required. One approach for completing the design change in a short time is to integrate dummy cells for allowing design change within the circuit to be designed in advance, as disclosed by Kumano et al. in Japanese Laid Open Patent Application No. JP-P2005-322694A. The dummy cells are spare cells which are originally unnecessary for the circuit to be designed, but used in case of design change if necessary.
In Japanese Laid Open Patent Application No. JP-P2006-128635A, Inoue discloses a technique in which spare scan flip-flop cells are preliminarily prepared in addition to scan flip-flop cells for allowing design change. The spare scan flip-flop cells are designed to have the same function as the normal scan flip-flop cells, and incorporated into the circuit to be designed when a design change is required. One issue is that the clock supply may be unbalanced when a clock line is newly connected to a spare scan flip-flop cell in the design change. In order to address this, the Inoue's technique performs clock tree synthesis for both of the normal scan flip-flop cells and the spare scan flip-flop cells. In the layout design, a clock tree circuit is connected to both of the normal scan flip-flop cells and the spare scan flip-flop cells. This allows supplying a timing-adjusted clock signal to both of the normal scan flip-flop cells and the spare scan flip-flop cells through the clock tree circuit.
According to the inventor's study, however, the Inoue's approach suffers from useless increase in the power consumption. In an integrated circuit designed in accordance with the Inoue's technique, a clock signal is fed not only to normal scan flip-flops but also to spare scan flip-flops. Therefore, the spare scan flip-flops are also operated in response to the clock signal in circuit operations. This leads to useless power consumption.
One possible approach for power consumption reduction is to additionally incorporate a clock gating circuit through which a clock signal is fed to the spare scan flip-flops. The clock gating circuit allows stopping the clock supply to the spare scan flip-flops in response to a control signal to thereby suppress the useless power consumption in circuit operations. However, the additionally-provided clock gating circuit requires the chip resource and increases the chip size.